1. Field of the Invention
The present invention relates generally to 40-Gb/s data, and in particular, to a 40-Gb/s clock and data recovery circuit in 0.18 μm CMOS technology.
2. Description of the Related Art
(Note: This application references a number of different publications as indicated throughout the specification by reference numbers enclosed in brackets, e.g., [x]. A list of these different publications ordered according to these reference numbers can be found below in the section entitled “References.” Each of these publications is incorporated by reference herein.)
Clock and data recovery (CDR) circuits operating at tens of gigabits per second pose difficult challenges with respect to speed, jitter, signal distribution, and power consumption. Half-rate 40-Gb/s CDR circuits have been implemented in bipolar technology [1,2], but they require 5 V supplies and draw 1.6 to 5 watts of power. (The work in [1] uses an external oscillator and 90° phase shifter.) On the other hand, the recent integration of 10-Gb/s receivers in CMOS technology [3] encourages further research on CMOS solutions for higher speeds, especially if it enables low-voltage, low-power realization. The present invention comprises a design and experimental verification of a 40-Gb/s phase-locked CDR circuit fabricated in 0.18-μm CMOS technology.